Various electrical circuits—such as switch-mode power converters and switch-mode power amplifiers—employ transistors that are controlled to operate as switches. The transistors employed in these “switch-based” circuits are often power field-effect transistors (FETs) that are switched ON and OFF under the control of a square wave or some other bi-level drive signal. To minimize switching losses and maximize energy efficiency as the power FETs are switched ON and OFF it is desirable to minimize the times it takes for the power FETs to transition between ON and OFF states. Unfortunately, power FETs have large input gate capacitors that must be charged in order to switch them from OFF to ON states but the drive signals, which are often generated by a logic circuit or other circuit, such as a microcontroller, often lack the current supplying capability necessary to rapidly charge the large input gate capacitors. To overcome this problem a gate driver is usually employed. As illustrated in FIG. 1, by using the gate driver 102 the large drive currents needed to rapidly charge the input gate capacitors of the power FETs is made possible and switching losses are thereby minimized.
Although a gate driver can help to minimize switching losses, it will not necessarily produce a drive signal Vdrive that is capable of switching the power FETs in the switch-based circuit between fully ON and fully OFF states. Switching the power FETs between fully ON and fully OFF states is important since it reduces I-R losses during times when the power FETs in the switch-based circuit 104 are conducting (ON) or blocking (OFF) current. A power FET will be turned fully ON when it is forced to operate in its linear region of operation (or “ohmic” region), where its ON resistance (drain-source resistance RDS(ON)) is very low, and will be turned fully OFF when it is forced to operate in its cut-off region of operation, where its OFF resistance is very high. In the case of an n-channel, enhancement mode power FET (e.g., a silicon, n-channel, enhancement mode metal-oxide-semiconductor FET (Si-MOSFET)), the power FET will be forced to operate in its cut-off region if the drive voltage applied to its gate VG is lower than the voltage applied to its source VS by at least the power FET's threshold voltage VT (i.e., if VG−VS=VGS<VT), and will be forced to operate in its linear region if the drive voltage applied to its gate VG is higher than the voltage applied to its drain VD by at least one threshold voltage VT and higher than the voltage applied to its source VS by at least one threshold voltage VT, in other words, if: VG−VS>VT and VG−VD>VT. Unfortunately, the high and low drive levels VH and VL of the drive signal Vdrive produced by the gate driver 102 are not always of the proper levels necessary to satisfy these requirements. This problem is highlighted in the signal diagram shown in FIG. 2, where it is seen that the high and low drive levels VH and VL of the drive signal Vdrive produced by the gate driver 102 in FIG. 1 are both higher than the acceptable input high-level and acceptable input low-level ranges of the power FET of the switch-based circuit 104 being driven. This incompatibility is unacceptable since it renders the gate driver 102 incapable of switching the power FET fully ON and fully OFF, as desired.
The incompatibility of the high and low drive levels VH and VL of the gate drive signal Vdrive at driving the power FET in the switch-based circuit 104 between fully ON and fully OFF states can be overcome in some situations by level shifting the drive signal Vdrive. The simplest approach to level shifting the drive signal Vdrive is to pass the drive signal Vdrive through a DC blocking capacitor 302, as illustrated in FIG. 3, and then to bias the resulting AC signal by a DC bias voltage VBIAS using a resistor 304. So long as the level-to-level voltage swing of the drive signal Vdrive is within certain limits, the high and low drive levels VH and VL of the resulting level-shifted drive signal Vdrive′ can be made to fall within the acceptable input high-level and acceptable low-level input ranges of the switch-based circuit being driven, as illustrated in FIG. 4.
The level-shifting approach in FIG. 3 is a suitable solution for many applications. However, it is not an acceptable solution in situations where the duty cycle of the drive signal Vdrive varies over time. This limitation deserves serious consideration since many types of switch-based circuits are driven by pulse-width modulation (PWM) signals, which have waveforms with time-varying duty cycles. For example, in a synchronous buck converter, which is an example of one type of switch-mode power converter, PWM signals are used to drive the high-side and low-side power FETs of the converter's half-bridge and the duty cycles of the PWM signals are varied to regulate power delivery to a load. Similarly, in a Class-D power amplifer which is an example of one type of switch-mode power amplifier, PWM signals are used to drive the high-side and low-side FETs of the amplifier's switching stage and the duty cycles of the PWM signals are modulated to encode and convey information (e.g., voice or data). If the conventional level-shifting approach depicted in FIG. 3 was to be used to level shift an input PWM signal Vdrive in these PWM applications, the resulting level-shifted PWM drive signal Vdrive′ would end up appearing similar to that shown in FIG. 6, where it is seen that the extent to which the level-shifted PWM drive signal Vdrive′ has been shifted depends on the duty cycle of the input PWM waveform VIN (compare FIGS. 5 and 6). This dependency follows from the fact that the DC component of the input PWM waveform VIN is higher the higher the duty cycle is (see FIG. 7). Employing the level-shifting approach in FIG. 3 to level-shift PWM signals would consequently result in the level-shifted drive signal Vdrive′ having high and low drive levels VH and VL that vary over time depending on the duty cycle D of the input switching signal VIN. This effect can be seen in the timing diagrams in FIGS. 5 and 6. Specifically, as the duty cycle D of the input switching signal VIN increases from 50% to 75% (see FIG. 5), the high and low drive levels VH and VL of the level-shifted PWM drive signal Vdrive′ both reduce in value from VH,1 and VL,1 to VH,2 and VL,2 (see FIG. 6), and as the duty cycle D of the input switching signal VIN subsequently decreases from 75% to 25%, the high and low drive levels both increase in value from VH,2 and VL,2 to VH,3 and VL,3. This dependency of the high and low drive levels VH and VL on the duty cycle D of the input PWM drive signal VIN is highly undesirable since, as can also be seen in FIG. 6, it can result in the high and low drive levels VH and VL not always falling within the acceptable input high-level and acceptable input low-level ranges of the switch-based circuit being driven. The only way to avoid this problem when the level-shifting approach depicted in FIG. 3 is being used is to severely constrain the extent to which the duty cycle D of the input switching signal VIN can vary.
Considering the drawbacks and limitations of conventional level-shifting approaches, it would be desirable to have level-shifting methods and apparatus that are not only capable of level shifting an input PWM gate drive signal but which are also capable of maintaining the high and low drive levels of the level-shifted PWM gate drive signal at fixed voltages, irrespective of changes made to the duty cycle of the input PWM gate drive signal.